In previous technology generations, DFM was implemented by design rules. A design rule clean tape-out meant delay free mask preparation, and error free silicon manufacturing. At 65nm and beyond, design rules are no longer sufficient for predictable manufacturability. Due to lithography issues and increased process variability, certain patterns that are DRC correct might not print properly on a wafer, resulting in severe yield degradation.
The rule-based paradigm that served the industry well through the 90nm generation, needs now to be complemented with a model-based approach. Physical design needs to be correct and optimized not only for design rules, but also for lithography and manufacturing models.
To make a physical design optimized for lithography, designers need a solution that optimizes their layout according to fab models. But it must work automatically with minimal involvement from them, as they need to focus their scarce resources on solving design issues.
Sagantec developed such a solution: DFM correction and optimization tools that are both rule-based and model-based. Using these tools, physical design can be automatically corrected and optimized resulting in shorter mask and silicon turnaround-time, no re-spins and higher silicon yield. |
